In general, as pixels made using CMOS processes scale to smaller dimensions, some performance properties of these smaller pixels degrade. Specifically, the photodiode capacity decreases. This reduces the dynamic range of the image sensor.
Some of the photodiode capacity can be gained back by moving from a non-shared pixel design as illustrated in FIG. 1 to a shared pixel design like the 4-shared pixel design illustrated in FIG. 2. The non-shared design of FIG. 1 includes a photodiode 1 that collects charge in response to light, and a transfer gate 2 for transferring charge from the photodiode 1 to a floating diffusion 3. A source follower amplifier 5 senses the charge, and in response, the source follower amplifier 5 passes its output signal onto an output line 8 via an output 9. A reset transistor 4 resets the floating diffusion 3 to a predetermined signal level, and a row select transistor 7 is selectively activated for passing the output of the source follower amplifier 5 to the output line 8.
Referring to FIG. 2, there is shown the shared pixel design having the same components as the non-shared except that the reset transistor 4, source follower amplifier 5, and row select transistor 7 are shared by multiple photodiodes 11, 12, 13 and 14 whose charge is transferred respectively by transfer gates 15, 16, 17 and 18. This reduces the number of transistors per pixel, which allows for a larger photodiode area and therefore a large photodiode capacity.
One drawback of shared pixel approach is an increase in the capacitance of the floating diffusions 19, 20, 21, and 22. Each pixel in the kernel adds capacitance since the floating diffusion nodes are wired together in parallel. As defined herein, a kernel is defined as the group of pixels sharing the same floating diffusion. Increasing the floating diffusion capacitance decreases the voltage-to-charge conversion ratio into the source follower amplifier 5. Increasing floating diffusion capacitance increases the electron read noise. Increasing electron read noise reduces dynamic range. However, for most applications, the positive benefits of increasing the photodiode area by moving to shared pixel architectures outweigh the negatives.
Feedback can be used to effectively reduce floating diffusion capacitance. As illustrated in FIG. 3a, there is shown the shared design as in FIG. 2 except that the floating diffusion wire 31 interconnecting the floating diffusions is physically above a shielding wire 30 as illustrated in FIG. 3b. The shielding wire 30 is electrically connected to the output 9 of the source follower (SF) amplifier 5. In another configuration not shown, the shielding wire is instead connected to Vout 8 of the row select transistor 7. Because the signal of output 9 follows the voltage on the floating diffusions 19, 20, 21, 22 with almost unity gain, the voltage on the shield follows the voltage on the floating diffusion. By shielding the floating diffusion wire 31 with a shield biased at Vout, the parasitic capacitance of the floating diffusion interconnect is reduced, resulting in an increase in the voltage-to-charge conversion ratio.
Recently, there has been a flurry of activity in 3D integration of the pixel by stacking two or more silicon wafers with electrical interconnects between the two wafers. An embodiment of this technology is illustrated in FIG. 4. This embodiment is the same as FIG. 2 except that the photodiodes 23a, 23b, 24a, and 24b and transfer gates 25a, 25b, 26a, and 26b are on the sensor wafer 40, and the remaining transistors are moved from the sensor wafer (SW) 40 and onto the circuit wafer (CW) 41 below the pixel. The photodiodes 23a, 23b, 24a, and 24b are contained in an active layer (silicon) 42 bounded by two dielectric layers 43 and 54. Moving the transistors to the active layer (silicon) 67 on the CW 41 increases the photodiode (PD) area, which increases PD capacity, and hence dynamic range. However, one of the negative aspects of this approach is that there is more parasitic floating diffusion capacitance due to the electrical interconnect 55 and electrical interconnect wire 52 between the two wafers.
Another negative of the 3D approaches illustrated in FIG. 4 is that there is more cross capacitance between floating diffusion wires, which leads to more electrical cross talk.
Consequently, a need exists for a pixel design which overcomes the above-described drawbacks.